lesson 1- Introduction, Binary Number, intro- install modelsim

Lab #1: Intro to modelSIM

lesson 2- Gates, Multiplexers

Lab #1: Continued

lessonĀ 3 -HDL overview, Entities, Architectures, Types, Concurrent Signal Assignment

Lab #2: Intro to Xilinx synthesis

lesson 4 – Processes, Sequential Statements

Lab #2: Continued

lesson 5- Flip-Flops, Registers, FSMs

Lab #3: 7-Segment Decoder

lesson 6 -Sequential Circuit Design: Principle, Time Analysis

Lab #3: Continued

Lab #3: Continued

Lab #3: Continued

Midterm Exam

lesson 7-FSMs and VHDL descriptions, ASM, Timing, Outputs, Glitches

Lab 4a: UART transmitter

lesson 8- Pinelining

Lab #4: Continued

lesson 9-RTL Design Overview

Lab #4: Continued

lesson 10 -Parameterized Design methods

Lab #4: Continued

lab #4: Continued

Lab #4: Continued

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