Please refer to the following books for assignments:
i. RTL Hardware Design Using VHDL Coding by Pong P. Chu
- Textbook problem 3.5. Demonstrate your answer via simulation using
Modelsim. You may use signals a, b, and c as the left hand sides of the
assignment statements so that you can do all 3 parts of this problem in a single
- Textbook problem 3.7. Demonstrate your answer via simulation using
- Code up and simulate, using Modelsim, a full-adder circuit. Do not include
delays in your signal assignment statements. Exercise the circuit using a .do file.
Be sure you exhaustively simulate it.
What to turn in:
For each problem, turn in printouts of your VHDL code and marked-up simulation
output waveforms along with answers to any questions posed in the assignment